I should probably mention that I had similar trouble several years ago when I was building my first Nixie clock. Since then, I've been inspired to build a clock using only discrete components, and I have everything except the timebase complete. The pulse source I came up with uses the idea of a zener diode to clip the 60Hz sine wave before passing it through a monostable multivibrator. Since I wouldn't be using a 74121, I used the basic circuit found via a Google search borrowed the time constant from the old Texas Instruments Nixie clock schematic. The square wave signal is then put through six T flip-flops wired so that they reset when they reach the binary equivalent of 60, using a 4-input and gate and a reed relay. The problem I'm having is that while the output from the monostable circuit shows up as a clean 60Hz square wave on my friend's nice oscilloscope, the last flip-flop is outputting a 1.04Hz pulse, causing the clock to gain at least 2 seconds per minute.
The schematic image shows the basic circuit minus the reset circuit and the last four flip-flops. My only thought is that the values of the components used in the flip-flops might be having an effect.
So I did some testing with the circuit and an Oscope and I'm still confused. I decided to test my circuit against a 7490 and a 7492 rigged to divide by 60. I attached the input of the divider to the output of my monostable circuit, and the output was still at 1.04Hz! I then attempted to bypass the monostable circuit by using a 7414 schmitt trigger as the input to the divider, and got the same result. Interestingly, if I measure the output of the flip-flop just before the last stage in the 7492, I see exactly 2.00Hz. The output of the 7490 was exactly 6.00Hz, which means that everything until the last flip-flop is good. My only guess is that something about the way my circuit and these TTL chips reset at the end of the count cycle causes the last stage to run slightly fast. At this point I think I'll just finish building the thing and call it good.
10 months 2 weeks ago - 10 months 2 weeks ago#7536by Ian
When you observe the circuit, do you read a constant frequency of 1.04Hz on every cycle, or is the 1.04Hz something you have calculated based on the fact it is running fast? Or are you perhaps inserting a count somewhere?
My suspicion is that there's a problem in the reset circuit. Perhaps a race condition meaning that it resets earlier than required under some circumstances?
I don't see how you might get from 2Hz to 1.04Hz on a per cycle basis...
Last Edit: 10 months 2 weeks ago by Ian. Reason: Corrected 10.4Hz -> 1.04Hz
The output is a steady 1.04Hz. I also tested my circuit against a crystal oscillator circuit with a 4060. After the 2Hz output from that was passed through the first divide-by-2 of a 7490, it came out as 1.04Hz. I don't get it. No matter what means I use to obtain a 1Hz signal, it always comes out as 1.04Hz.
So here's the basic reset circuit. Once the last four flip flops reach the Q=1 state, the relay pulls in and grounds all of the Q outputs through 1N4148 diodes causing them to hold at Q=0. What I'm wondering is, is it possible that the relay takes too long to pull in, allowing the first few stages to start turning on? I appreciate the help.
Ill give that a shot here soon. That was the approach I first took to this project, but found that unless the reset was held low for a certain amount of time the flip-flops wouldn't completely reset. However, that was in situations where one flip-flop resetting would result in the next one turning on after the reset pulse. I've also found that increasing the value of the capacitor on the relay causes the output frequency to drop slightly as the value gets larger.
Yep, what Ian said. Also keep in mind that mechanical relay contacts "bounce" when they change state. Contact bounce is too fast and random to easily perceive (looks like a little noise burst on the scope, if noticed at all) but the TTL stuff will see it and react to it in a somewhat strange and unpleasant manner, e.g. intermittently getting false resets or false counts...
Look into it later when the dust is clearing off the crater.
Thinking about it a bit more, the capacitor is also a problem. This will hold the reset line low for a period of time even after the reset has propagated.
In any case, the answer is the same, need to go solid state.
I'll be building an all transistor clock soon from KABTronics (It will be a full build review), and might have some more input when I have looked at the manuals, but at first glance, it looks largely like what I sketched above.
They do it as a divide by 10 and a divide by 6, but each stage with a PNP reset transistor.
Thanks for the replies guys! I actually discovered a few other issues when implementing the solid state circuit. When the last three stages were at Q=1, as the third stage stage went to Q=1, the very last flip-flop would abruptly shut off. This was without the reset hooked up. I discovered that disconnecting the Q output connection from the last stage to the reset transistor AND gate assembly prevented it from doing this. I then decided to use a simpler approach, and built a 4-input AND gate using diodes, which provided a good output when the last four stages went high without disrupting the very last stage. Now, however, I have a different problem. With the last two flip-flops in the 1 state, as the (8) flip-flop transitions to a 1, the (4) flip-flop is also briefly at 1 while changing to a 0, and since this satisfies the condition the AND gate wants for a split second, it resets the circuit. I'm wondering if inducing a delay between the (4) and (8) flip-flops would prevent this condition from occurring, allowing (4) to go to 0 before the next stage transitions to 1? I appreciate the advice you've all been giving me.